This invention relates generally to integrated circuits.
Integrated circuits include input pins for receiving signals from the outside world and output pins for providing signals to the outside world. Since integrated circuit packages are advantageously compact, increasing the number of pins means increasing the integrated circuit packaging size and cost.
For example, when testing integrated circuits, a number of modules or components may be scanned or analyzed for errors or defects. The more scan chains of modules to be analyzed, generally the more pins that are needed to receive signals from those scan chains. Conversely, the longer the scan chains, the slower the testing process. Either way, the costs may be aggravated.
Some of the major contributors to integrated circuit test cost include: available tester memory, available number of tester channels, test time, and number of pins available for scan-in and scan-out purposes. All these contributors to test cost have direct relationships with the scan chain lengths and the number of scan chains.
Therefore, there is a need for better ways to compact circuit outputs to reduce the number of circuit pins or connectors without increasing the size of the circuit elements.